1-D and 2-D hot carrier layout optimization of N-LDMOS transistor arrays

Today´s power management devices often require operation in the 20-30 V range. These applications often combine a high performance BiCMOS process with a power lateral DMOS (LDMOS) driver. To obtain high drive current density and minimal on-resistance (Rdson), LDMOS devices are often implemented in transistor arrays. Because of the high voltages and currents applied to these LDMOS arrays hot carrier (HC) degradation is a real reliability concern. This paper focuses on improving the HC reliability of N-LDMOS transistor arrays. Layout optimization is emphasized since the LDMOS and Bipolar/CMOS devices share common process steps. This paper differs from previous work in that it discusses for the first time the one- and two-dimensional aspects of LDMOS transistor array layout on HC performance. In addition this paper introduces for the first time a novel LDMOS transistor layout featuring a Drain Ring that dramatically improves the HC performance of these arrays.