Title :
Timing-driven partitioning for two-phase domino and mixed static/domino implementations
Author :
Min Zhao ; Sapatnekar, S.S.
Author_Institution :
Minnesota Univ., Minneapolis, MN, USA
Abstract :
Domino logic is a high-performance circuit configuration that is usually embedded in a static logic environment and tightly coupled with the clocking scheme. In this paper the timing-driven partitioning algorithms that partition a logic network between (1) static and domino implementations, and (2) the phases of a two-phase clock, are provided In addition, an efficient static mapping algorithm is described.
Keywords :
clocks; logic CAD; logic partitioning; timing; clocking scheme; domino logic; high-performance circuit configuration; logic network partitioning; mixed static/domino implementation; static logic environment; static mapping algorithm; timing-driven partitioning; timing-driven partitioning algorithm; two-phase clock; two-phase domino implementation; Circuit synthesis; Clocks; Combinational circuits; Cost function; Logic circuits; Logic design; Network synthesis; Partitioning algorithms; Space technology; Timing;
Conference_Titel :
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-5832-5
DOI :
10.1109/ICCAD.1999.810631
