Title :
A 250MHz-to-4GHz Δ-Σ fractional-N frequency synthesizer with adjustable duty cycle
Author :
Huang, Chen-Wei ; Gui, Ping
Author_Institution :
Dept. of Electr. Eng., Southern Methodist Univ., Dallas, TX, USA
fDate :
May 30 2010-June 2 2010
Abstract :
A Δ-Σ fractional-N Phase-locked Loops (PLL)- based frequency synthesizer (FS) with a frequency range of 250 MHz to 4 GHz is presented. By employing the Δ-Σ fractional-N technique and utilizing the multi-phase clocks available in the ring-VCO of the PLL, the frequency synthesizer is capable of generating high-resolution and low-spur clocks with instant frequency switching. Moreover, the proposed FS has the ability to adjust clock duty cycle which is needed in applications such as time-interleaved ADCs, switched-capacitor circuits, and DC-DC converters.
Keywords :
frequency synthesizers; modulators; phase locked loops; sigma-delta modulation; voltage-controlled oscillators; adjustable duty cycle; clock duty cycle; delta-sigma fractional-N frequency synthesizer; delta-sigma fractional-N phase-locked loops; frequency 250 MHz; frequency 4 GHz; multi phase clock; ring VCO; Circuits; Clocks; DC-DC power converters; Frequency synthesizers; Jitter; Phase locked loops; Semiconductor device noise; Switching converters; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537789
