A novel double RESURF LDMOS with optimized ESD robustness

In this paper, a double RESURF LDMOS with optimized ESD robustness is proposed. By implanting P+ at the drain region, an additional discharge path through a vertical PNP is formed. The current density at the source side is reduced, thus it restrains the triggering of the parasitic lateral NPN. The discharge limits under ESD stress of this structure is altered from the triggering of the parasitic lateral NPN to the second breakdown of the parasitic vertical PNP. Contrast to the conventional structure, the discharge ability of the novel device increases form 1.57times10_-5 Amum_-1 to 3.13times10_-5 Amum_-1.