A low-power 6-bit D/A converter design for WSN transceivers

Author

Li, Yuanliang ; Li, Zhiqun

Author_Institution

Inst. of RF- & OE-ICs, Southeast Univ., Nanjing, China

fYear

2011

fDate

25-28 Sept. 2011

Firstpage

307

Lastpage

310

Abstract

This paper presents a 6-bit 1.8V 16MS/s, low-power digital to analog converter (DAC) using TSMC 0.18μm CMOS technology for WSN applications. It is based on a current steering binary weighted architecture. It has differential current outputs. The output voltage is externally generated by the current that the DAC injects into high precision resistor. The DAC occupies 0.7mm×0.5mm. A spurious-free dynamic range (SFDR) of more than 50dB has been simulated over the complete Nyquist interval at sampling frequencies up to 16MS/s. The power consumption at a 16MHz clock frequency for a near-Nyquist sinusoidal output signal approximately equals 1.5mW.

Keywords

CMOS digital integrated circuits; Nyquist criterion; digital-analogue conversion; power consumption; radio transceivers; wireless sensor networks; CMOS technology; DAC; SFDR; TSMC; WSN transceivers; digital to analog converter; low-power 6-bit D/A converter design; near-Nyquist sinusoidal output signal; power consumption; spurious-free dynamic range; voltage 1.8 V; CMOS integrated circuits; Clocks; Layout; Power demand; Transceivers; Transistors; Wireless sensor networks; CMOS; Current-steering; D/A converters; DAC; SFDR; WSN;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Technology (ICCT), 2011 IEEE 13th International Conference on

Conference_Location

Jinan

Print_ISBN

978-1-61284-306-3

Type

conf

DOI

10.1109/ICCT.2011.6157885

Filename

6157885