High-performance chip-to-chip signaling

Summary form only given. High-performance chip-to-chip signaling is a challenging requirement of many modern VLSI systems and with ITRS predictions of 160-Gb/s serial I/O and 40-Gb/s parallel I/O links by 2016 it is likely to remain so. There has recently been a proliferation of signaling standards such as PCI Express, XAUI, RapidIO, Interlaken, and others making it difficult for practicing engineers and researchers to keep up. This tutorial presents the fundamentals of chip-to-chip signaling enabling attendees to understand and meet the requirements of these technologies. The most pressing research challenges in chip-to-chip signaling are also covered, so that by the end of the session attendees are up to speed with the state-of-the-art. First, the requirements and specifications of chip-to-chip links are introduced. Particular attention is paid to signal integrity. Modeling and simulation methodologies that include the effects of trace losses, link discontinuities, clock jitter, and noise are presented enabling attendees to accurately estimate bit error rates over complex links. We will then proceed to circuit architectures for transmitters and receivers. The presenter is an active researcher in highspeed equalization and clock recovery, so these will be areas of focus. Any engineers working with multi-Gb/s digital signals will benefit by gaining an understanding of signal specifications, signal integrity, and clocking architectures. Chip-to-chip signaling researchers will gain insights into advanced modeling techniques and high-speed equalization and timing recovery architectures.