4C: IP Session - High Speed I/O Test [breaker page]

High-speed I/Os (inputs/outputs), transmitting and receiving data in Multi-Gbps speeds, are becoming commonplace in many system and chip-to-chip communication applications. The different nature of such I/Os from the lower-speed parallel ones, high volumes, and deployment of hundreds of these I/Os on a single chip pose new test and yield challenges for cost-effective production of many today??s and future ICs. Such challenges include testing signal integrity parameters, i.e., jitter, voltage, and impedance, especially in the presence of pre- or de-emphasis and receiver equalization. The "high-speed I/O test" innovative practices track includes three presentations to discuss such challenges and provide solutions. First presenter will discuss SUN Microsystems approach for yield enhancement and test of devices with tens and hundreds of high-speed I/Os. The second speaker will address signal integrity test issues, and the third contributor will provide an ATE perspective of test challenges and possible solutions.