A synthesizable on-chip wormhole router

Multi-core may afford the computation capacity for the computation-intensive tasks, such as machine learning. In such a chip, the inter-cores communication is one of the greatest challenges. A synthesizable wormhole router was proposed for the emerging inter-cores communication scheme, i.e. network-on-chip (NoC). The proposed router not only offers common configurable parameters including buffers, virtual-channels and routing algorithms, but also has its inner-pipeline parameterized. The pipeline may be organized as the conventional 3-stage one, 4-stage one or the in-house 5-stage one. The 5-stage pipelining scheme is a variation of the 4-stage one, but has the longest stage for virtual-channel allocation in the ancestor split into two stages. Then it may achieve higher maximum frequency. The packet latency in a wormhole-switch network was decomposed, and the impact from pipelining scheme and the number of virtual-channels was evaluated. A principle was proposed for on-chip router design, which arouses higher frequency for more performance and less packet latency.