DocumentCode :
3387554
Title :
Fault modeling and simulation for crosstalk in system-on-chip interconnects
Author :
Cuviello, M. ; Dey, S. ; Xiaoliang Bai ; Yi Zhao
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
fYear :
1999
fDate :
7-11 Nov. 1999
Firstpage :
297
Lastpage :
303
Abstract :
System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies, as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects in GHz SOCs, we address in this paper the problem of testing for glitch and delay errors caused by crosstalk in buses and interconnects between components of a SOC. Since it is not possible to explicitly test for all the possible process variations and defects that can lead to crosstalk errors in SOC interconnects, we present an abstract model, Maximum Aggressor (MA) fault model, and its test requirements. The attractiveness of the model is that it can abstract crosstalk defects in interconnects with a linear number of faults, while the corresponding MA tests provide complete coverage for all level defects related to cross-coupling capacitance the interconnects. A SPICE-level fault simulation methodology is presented which allows simulation of a small subset of the potentially exponential number of defects. The simulation methodology also enables validation of the proposed fault model and the resulting test set.
Keywords :
SPICE; crosstalk; fault simulation; integrated circuit interconnections; GHz clock frequencies; SPICE-level fault simulation; abstract model; crosstalk; delay errors; fault modeling; simulation; system-on-chip interconnects; Capacitance; Circuit faults; Circuit testing; Clocks; Conductors; Crosstalk; Inductance; Integrated circuit interconnections; Signal design; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-7803-5832-5
Type :
conf
DOI :
10.1109/ICCAD.1999.810665
Filename :
810665
Link To Document :
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