A statistical method for correlating in-line defectivity to probe yield

Improving yield in semiconductor production requires continuous effort and the application of complex fools. The task is further complicated when new products with smaller dimensions are introduced. Popular methods for identitfying yield enhancement opportunities include defect map overlays, trend charts, failure analysis, defect source analysis, paretos of classified defects and killer defect classification. Statistical methods for yield enhancement offer another choice of analysis techniques. The statistical method described here uses both the electrical bin failures from probe and the defects found with in-line inspections. The probability that defects added at each inspection result in a bin failure at probe is calculated. The correlation includes all of the wafers inspected in-line and covers both ASIC and BiCMOS products. A killer factor is determined for each level of inspection by defect type. Using this data, a six sigma defect density specification is set for each layer so that corrective actions can be taken before there is a significant yield impact at probe. The data also identifies layers with high killer factors as areas of focus for yield enhancement. A case study is presented with the correlation of defects by layer and by classification. The statistical method provides valuable information that can be used to identify opportunities for yield improvement and set SPC limits on in line measurements. The numerical format provides solid information to supplement the softer methods typically used in yield and defect analysis