DocumentCode :
3387591
Title :
Reductions of instantaneous power by ripple scan clocking
Author :
Joshi, Kirti ; MacDonald, Eric
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas at El Paso, TX, USA
fYear :
2005
fDate :
1-5 May 2005
Firstpage :
271
Lastpage :
276
Abstract :
The exponential increase in the number of transistors implemented in integrated circuits in each new generation of CMOS technology is causing an explosion not only in functional power consumption but in test power consumption as well. Although most research has focused mainly on reducing average power or the total energy consumed during test, instantaneous power consumption is also increasing and posing a serious threat for the ability of a chip to be tested in a manufacturing test floor - or worse in field testing using built-in-self test (BIST) where battery-powered applications lack the supply voltage robustness of automated test equipment (ATE). In this paper, a flip-flop design is proposed that is the cornerstone of a novel scan clocking architecture inspired by the need to reduce instantaneous power during scan.
Keywords :
CMOS integrated circuits; built-in self test; clocks; flip-flops; integrated circuit testing; logic testing; CMOS technology; automated test equipment; battery-powered applications; built-in-self test; field testing; flip-flop design; functional power consumption; instantaneous power consumption; instantaneous power reduction; manufacturing test floor; ripple scan clocking; test power consumption; Automatic testing; CMOS integrated circuits; CMOS technology; Circuit testing; Clocks; Energy consumption; Explosions; Integrated circuit technology; Integrated circuit testing; Power generation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
ISSN :
1093-0167
Print_ISBN :
0-7695-2314-5
Type :
conf
DOI :
10.1109/VTS.2005.71
Filename :
1443435
Link To Document :
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