DocumentCode
3387617
Title
A power amplifier with minimal efficiency degradation under back-off
Author
Singhal, Nitesh ; Nidhi, Nitin ; Pamarti, Sudhakar
Author_Institution
Henry Samueli Sch. of Eng. & Appl. Sci., Univ. of California, Los Angeles, Los Angeles, CA, USA
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
1851
Lastpage
1854
Abstract
A zero voltage switching technique that can maintain its peak efficiency over a 12dB dynamic range of output power is presented. The application of the technique is illustrated by the design and simulation based verification of an 800 MHz, 130nm CMOS PA that achieves close to a constant drain efficiency of about 40% over a 12 dB dynamic range of output power. System level simulations show that the PA achieves an ACPR of -54dBc at 400 KHz and -60dBc at 600 KHz frequency offsets respectively.
Keywords
CMOS integrated circuits; power amplifiers; CMOS PA; drain efficiency; frequency 400 kHz; frequency 600 kHz; frequency 800 MHz; power amplifier; size 130 nm; zero voltage switching technique; Bandwidth; Degradation; Digital modulation; Dynamic range; Maintenance engineering; Power amplifiers; Power engineering and energy; Power generation; Regulators; Zero voltage switching;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5537819
Filename
5537819
Link To Document