Title :
Survey of design and process failure modes for high-speed SerDes in nanometer CMOS
Author_Institution :
Metrologic Instruments, Blackwood, NJ, USA
Abstract :
This paper gives an overview of reported design-and process-related electrical performance failure modes for high-speed (> 1 GHz) serial interfaces fabricated using CMOS processes ≤130 nm. Effects of various defects on observable performance at the I/O pins are summarized, along with ATE test technology implications.
Keywords :
CMOS integrated circuits; automatic test equipment; failure analysis; integrated circuit testing; nanotechnology; peripheral interfaces; ATE test technology; CMOS processes; design-related failure modes; electrical performance failure modes; high-speed SerDes; nanometer CMOS; process-related failure modes; serial interfaces; Application specific integrated circuits; Built-in self-test; CMOS process; CMOS technology; Circuit testing; Clocks; Costs; Jitter; Process design; System-on-a-chip;
Conference_Titel :
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
Print_ISBN :
0-7695-2314-5
DOI :
10.1109/VTS.2005.79
