Title :
Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS
Author :
Chen, Qikai ; Mahmoodi, Hamid ; Bhunia, Swarup ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
In this paper, we have made a complete analysis of the emerging SRAM failure mechanisms due to process variations and mapped them to fault models. We have proposed two efficient test solutions for the process variation related failures in SRAM: (a) modification of March sequence, and (b) a low-overhead DFT circuit to complement the March test for an overall test time reduction of 29%, compared to the existing test technique with similar fault coverage.
Keywords :
CMOS memory circuits; SRAM chips; design for testability; failure analysis; integrated circuit modelling; integrated circuit testing; nanotechnology; March sequence; SRAM; efficient test solutions; failure mechanisms; fault coverage; fault models; low-overhead DFT circuit; nanoscale CMOS; process variations; test time reduction; CMOS process; Failure analysis; Random access memory; Semiconductor device modeling; Testing; Very large scale integration; DFT; Failure mechanixm; March Test; Process Variation; SRAM;
Conference_Titel :
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
Print_ISBN :
0-7695-2314-5
DOI :
10.1109/VTS.2005.58
