Title :
VLSI implementation of a quasi-ml, energy efficient fixed complexity sphere decoder for MIMO communication system
Author :
Lee, Kelvin ; Daneshrad, Babak
Author_Institution :
EE Dept., Univ. of California, Los Angeles, CA, USA
fDate :
May 30 2010-June 2 2010
Abstract :
This paper presents a low power VLSI implementation of a novel Multiple-Input Multiple-Output (MIMO) decoder which combines Fixed Complexity Sphere Decoder (FSD) algorithm, real-valued lattice formulation and Pair-wise sorted QR decomposition (P-SQRD) searching approach to simultaneously improve the throughput, bit error rate (BER) and complexity. Two-stage approximate sorting scheme with minimum data swapping is adopted to realize a power efficient architecture. This ASIC is implemented in IBM 90 nm 8 metal layer standard CMOS technology with core area of 1.3 mm2. This design supports 4×4 antenna array with flexible modulations from BPSK to 16-QAM. At 0.8V core power supply, the estimated peak data rate exceeds 1.44Gbps. The estimated energy efficiency is 15.4 pJ/bit which is 50% better than the other state of the art SDs.
Keywords :
MIMO communication; VLSI; antenna arrays; error statistics; BPSK; CMOS technology; MIMO communication system; VLSI implementation; antenna array; bit error rate; data swapping; fixed complexity sphere decoder algorithm; multiple input multiple output decoder; pairwise sorted QR decomposition searching approach; power efficient architecture; voltage 0.8 V; Application specific integrated circuits; Bit error rate; CMOS technology; Decoding; Energy efficiency; Lattices; MIMO; Sorting; Throughput; Very large scale integration;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537824
