Closed-form simulation and robustness models for SEU-tolerant design

Author

Mohanram, Kartik

Author_Institution

Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA

fYear

2005

fDate

1-5 May 2005

Firstpage

327

Lastpage

333

Abstract

A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SPICE-based calibration of logic gates for a range of values of fanout, charge, and scale factor is presented. A full set of experimental results demonstrate that on average, the model is accurate to within 5% of the results obtained using SPICE with over 100× improvement in computational speed. Besides simulation and analysis of SEU-induced transients, the proposed model can be used to perform reliability-aware logic synthesis through the incorporation of robustness metrics to tune cell libraries.

Keywords

SPICE; circuit simulation; integrated circuit design; integrated circuit modelling; integrated circuit reliability; logic circuits; logic design; logic gates; transient analysis; SEU-tolerant design; SPICE-based calibration; cell libraries; closed-form model; closed-form simulation; computational speed improvement; linear RC model; logic circuits; logic gates; reliability-aware logic synthesis; robustness metrics; robustness models; single-event upsets; voltage transients; Analytical models; Calibration; Circuit simulation; Logic circuits; Logic gates; Robustness; SPICE; Single event transient; Transient analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2005. Proceedings. 23rd IEEE

ISSN

1093-0167

Print_ISBN

0-7695-2314-5

Type

conf

DOI

10.1109/VTS.2005.35

Filename

1443445