Title :
Fast low power translation lookaside buffers using hierarchical NAND match lines
Author :
Clark, Lawrence T. ; Chaudhary, Vikas
Author_Institution :
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
fDate :
May 30 2010-June 2 2010
Abstract :
Translation lookaside buffers (TLB) are an essential component to speed up virtual to physical address translation in modern microprocessors. Here, hierarchical NAND content addressable memory (CAM) match lines are used to achieve low power. Simulations on a 65 nm foundry process show single-cycle accesses with a clock to physical address output delay of 168 ps. For large (16MB) page sizes the match line energy is reduced up to 81% compared to NOR match lines.
Keywords :
NAND circuits; buffer circuits; low-power electronics; microprocessor chips; hierarchical NAND content addressable memory match lines; low power translation lookaside buffers; microprocessors; size 65 nm; virtual-physical address translation; Associative memory; CADCAM; Circuits; Clocks; Computer aided manufacturing; Delay; Foundries; Microprocessors; Permission; Radio frequency;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537832
