Sense amplifier with offset mismatch calibration for sub 1-V DRAM core operation

In this paper, a sense amplifier circuit, which aims to operate with 1V or less supply voltage, is presented. While a conventional sense amplifier uses inverters connected in a cross-coupled manner without any special timing phase, the proposed sense amplifier circuit employs a calibration phase to provide offset voltage margin relaxation. The relaxed amount can be utilized for lowering Vcore, the DRAM core voltage, or increasing the number of Wordlines per Bitline. Also, it can be used for ensuring correct data operations in DRAM fabricated with severer process variation.