Title :
A compact and low power logic design for multi-pillar vertical MOSFETs
Author :
Sakui, Koji ; Endoh, Tetsuo
Author_Institution :
Center for Interdiscipl. Res., Tohoku Univ., Sendai, Japan
fDate :
May 30 2010-June 2 2010
Abstract :
The compact and low power logic circuit design for multi-pillar vertical MOSFETs has been proposed. The proposed design with the multi-pillar vertical MOSFETs is very practical for considering the load capacitance and resistance by changing the number of the silicon pillars flexibly for the desired channel width of series connected MOSFETs and their layout pattern.
Keywords :
MOSFET; logic circuits; logic design; channel width; compact low power logic design; layout pattern; load capacitance; load resistance; low power logic circuit design; multipillar vertical MOSFET; series connected MOSFET; Capacitance; Circuit synthesis; Contact resistance; Data mining; Delay effects; Immune system; Logic circuits; Logic design; MOSFETs; Silicon;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537837
