• DocumentCode
    3388027
  • Title

    Is wire tapering worthwhile?

  • Author

    Alpert, C.J. ; Devgan, A. ; Quay, S.T.

  • Author_Institution
    IBM Austin Res. Lab., TX, USA
  • fYear
    1999
  • fDate
    7-11 Nov. 1999
  • Firstpage
    430
  • Lastpage
    435
  • Abstract
    Wire sizing and buffer insertion/sizing are critical optimizations in deep submicron design. The past years have seen several studies of buffer insertion, wire sizing, and their simultaneous optimization. When wiring long interconnect, tapering, i.e., reducing the wire width as the distance from the driver increases, has proven effective. However tapering is not widely utilized in industry since it is difficult to integrate into a complete routing methodology. The article examines the benefits of wire sizing with tapering when combined with buffer insertion. We perform several experiments with actual IBM technologies. Results indicate that wire tapering reduces delay typically by less than 5% compared to uniform wire sizing, when buffers can be inserted. Consequently, we suggest that it may not be worthwhile to maintain a routing methodology that supports wire tapering.
  • Keywords
    circuit CAD; circuit optimisation; wires (electric); IBM technologies; buffer insertion; buffer insertion/sizing; buffers; critical optimizations; deep submicron design; long interconnect; routing methodology; uniform wire sizing; wire sizing; wire tapering; wire width reduction; Capacitance; Delay effects; Design optimization; Iterative algorithms; Laboratories; Logic; Quadratic programming; Timing; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • ISSN
    1092-3152
  • Print_ISBN
    0-7803-5832-5
  • Type

    conf

  • DOI
    10.1109/ICCAD.1999.810689
  • Filename
    810689