A low-power cell-based-design multi-port register file in 65nm CMOS technology

Author

Uhlig, Johannes ; Hoppner, Sebastian ; Ellguth, Georg ; Schüffny, René

Author_Institution

Dept. of Electr. Eng., Tech. Univ. Dresden, Dresden, Germany

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

313

Lastpage

316

Abstract

This paper presents the design of a register file with 4 write and 6 read ports for an SDR multiprocessor in 65nm CMOS technology. A cell-based design (CBD) methodology is employed in which the circuit is partitioned into complex sub-cells, optimized on transistor level and layout. Each cell is completely characterized concerning timing and power for seamless integration into a semi-custom design flow. The CBD implementation shows 30% savings of power and 40% of area compared to a conventional semi-custom solution. The average power is 2.7mW from 1.0V supply and 300MHz operating frequency which is superior to previously published designs.

Keywords

CMOS integrated circuits; integrated circuit design; low-power electronics; CMOS technology; SDR multiprocessor; frequency 300 MHz; low-power cell-based-design; multiport register file; power 2.7 mW; size 65 nm; voltage 1.0 V; CMOS technology; Circuits; Clocks; Latches; Logic testing; Paper technology; Radio frequency; Registers; Software libraries; Timing; cell-based design; low-power; register file;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537838

Filename

5537838