Title :
Segmented addressable scan architecture
Author :
Al-Yamani, Ahmad ; Chmelar, Erik ; Grinchuck, Mikhail
Author_Institution :
TNT, LSI Logic Corp., Milpitas, CA, USA
Abstract :
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consumption, and tester channel requirements. With minimal hardware overhead, the architecture provides at least an order of magnitude reduction to each of the above problems. The architecture relies on scan chain segmentation and multiple-hot decoders.
Keywords :
boundary scan testing; design for testability; digital integrated circuits; flip-flops; integrated circuit testing; digital IC testing; minimal hardware overhead; multiple problems; multiple-hot decoders; power consumption; scan chain segmentation; segmented addressable scan architecture; test architecture; tester channel requirements; Circuit testing; Clocks; Decoding; Design for testability; Energy consumption; Flip-flops; Instruction sets; Integrated circuit testing; Large scale integration; Logic testing;
Conference_Titel :
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
Print_ISBN :
0-7695-2314-5
DOI :
10.1109/VTS.2005.74
