DocumentCode
3388141
Title
Efficient diagnosis of path delay faults in digital logic circuits
Author
Pant, P. ; Chatterjee, A.
Author_Institution
Georgia Inst. of Technol., Atlanta, GA, USA
fYear
1999
fDate
7-11 Nov. 1999
Firstpage
471
Lastpage
475
Abstract
A novel methodology involving effect-cause analysis has been demonstrated for the diagnosis of path delay faults. We seek to provide an improved understanding of the methods introduced by Y.-C. Hsu and S.K. Gupta (1998), with the goal of devising efficient representations and algorithms for the diagnosis of path delay faults. Results indicate that the diagnostic resolution obtained is very high and includes all possible causes of the observed delay faults.
Keywords
fault diagnosis; logic CAD; logic testing; diagnostic resolution; digital logic circuits; effect-cause analysis; efficient diagnosis; observed delay faults; path delay fault diagnosis; Circuit faults; Circuit testing; Delay effects; Digital integrated circuits; Fault diagnosis; Integrated circuit testing; Logic circuits; Predictive models; Robustness; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-7803-5832-5
Type
conf
DOI
10.1109/ICCAD.1999.810696
Filename
810696
Link To Document