Title :
Pattern generation and estimation for power supply noise analysis
Author :
Nourani, Mehrdad ; Tehranipoor, Mohammad ; Ahmed, Nisar
Author_Institution :
Dept. of EE, Univ. of Texas at Dallas, TX, USA
Abstract :
This paper presents an automatic pattern generation methodology to stimulate the maximum power supply noise in deep submicron CMOS circuits. Our ATPG-based approach first generates the required patterns to cover 0 → 1 and 1 → 0 transitions on each node of internal circuitry. Then, we apply a greedy heuristic to find the worst-case (maximum) instantaneous current and stimulate maximum switching activity inside the circuit. The quality of these patterns was verified by SPICE simulation. Experimental results show that the pattern pair generated by this approach produces a tight lower bound on the maximum power supply noise.
Keywords :
CMOS integrated circuits; SPICE; automatic test pattern generation; circuit simulation; greedy algorithms; integrated circuit noise; integrated circuit testing; power supply circuits; ATPG; CMOS circuits; SPICE simulation; automatic pattern generation; greedy heuristic; internal circuitry; pattern estimation; power supply noise analysis; switching activity; Circuit noise; Libraries; Noise generators; Pattern analysis; Power generation; Power supplies; RLC circuits; SPICE; Switching circuits; Voltage;
Conference_Titel :
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
Print_ISBN :
0-7695-2314-5
DOI :
10.1109/VTS.2005.65
