DocumentCode :
3388283
Title :
A high power-added efficiency GaAs power MESFET operating at a very low drain bias for use in L-band medium-power amplifiers
Author :
Murai, S. ; Sawai, T. ; Yamaguchi, T. ; Matsushita, S. ; Harada, Y.
Author_Institution :
Sanyo Electric Co. Ltd., Osaka, Japan
fYear :
1997
fDate :
4-7 Oct. 1997
Firstpage :
139
Lastpage :
142
Abstract :
A power MESFET offering a high eta /sub add/ operating at a very low V/sub DD/ has been developed. The MESFET has a buried p-layer and an improved LDD (lightly doped drain) n+ self-aligned structure which include highly electrically activated ion-implanted regions due to rapid thermal-cap annealing using double-layered SiN films deposited by ECR plasma chemical vapor deposition. The device geometries and implantation conditions were optimized to achieve a high V/sub (BR)GDO/ of more than 10 V and a low V/sub K/ of less than 0.5 V, and to minimize the bias dependence of S-parameters. This produced excellent electrical characteristics such as P/sub 0(1dB/)=177 mW (173 mW), eta /sub add/=38.8% (32.6%) at V/sub DD/=3 V (2 V), and I/sub DS/=0.16 A ( approximately 0.4I/sub DSS/) (0.24 A ( approximately 0.6I/sub DSS/)) at 1.9 GHz.<>
Keywords :
III-V semiconductors; S-parameters; Schottky gate field effect transistors; gallium arsenide; incoherent light annealing; ion implantation; microwave amplifiers; plasma CVD; power amplifiers; power transistors; rapid thermal processing; solid-state microwave devices; 0.16 A; 0.24 A; 1.9 GHz; 173 mW; 177 mW; 2 V; 3 V; 38.8 percent; ECR plasma chemical vapor deposition; GaAs-SiN; L-band medium-power amplifiers; LDD; S-parameters; bias dependence; buried p-layer; device geometries; double layered film; drain bias; electrical characteristics; high power-added efficiency; ion implantation; lightly doped drain; power MESFET; rapid thermal-cap annealing; self-aligned structure; semiconductor; Chemical vapor deposition; Decision support systems; Gallium arsenide; Geometry; MESFETs; Plasma chemistry; Plasma devices; Rapid thermal annealing; Silicon compounds; Time of arrival estimation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1992. Technical Digest 1992., 14th Annual IEEE
Conference_Location :
Miami Beach, FL, USA
Print_ISBN :
0-7803-0773-9
Type :
conf
DOI :
10.1109/GAAS.1992.247205
Filename :
247205
Link To Document :
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