Title :
Steps per wafer reduction for photolithographic tool productivity improvement
Author :
Sisler, S.B. ; Bonn, J.P. ; Whiteside, R.C.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
This paper describes progress at the IBM Microelectronics Division semiconductor fabricators to improve photolithographic (litho) tool productivity by reducing the number of exposure steps per wafer. A cost-based algorithm that guides device designers to aspect ratios which minimize litho processing costs is described. A similar algorithm which finds optimum chip matrices for various types of litho tools is also presented, while various options for improving chip matrixing are explored
Keywords :
costing; integrated circuit manufacture; photolithography; IC manufacture; aspect ratios; cost-based algorithm; exposure steps; optimum chip matrices; photolithographic tool; processing costs minimisation; semiconductor production; steps per wafer reduction; tool productivity improvement; Chip scale packaging; Lenses; Logistics; Manufacturing; Microelectronics; Postal services; Productivity; Rivers; Shape; Telephony;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-4050-7
DOI :
10.1109/ASMC.1997.630713
