Precise area-controlled return-to-zero current steering DAC with reduced sensitivity to clock jitter

A precise return-to-zero current steering DAC is presented. This architecture uses a scaled switched-capacitor replica and a comparator to integrate the current over time, resulting in an accurate pulse. Without significant increase in the pulse height, the generated pulse can have its minimal value at the end of the DAC phase, hence minimizing the clock jitter effect. The proposed DAC can be used in continuous-time delta-sigma modulators to achieve high accuracy even in presence of the clock jitter. Simulation results are provided to prove the efficiency of this structure.