A stacked DCFL structure applied to a prescalar IC and investigated for ASICs

Author

Shimizu, S. ; Kamatani, Y. ; Koide, N. ; Nagasawa, H. ; Kataoka, S. ; Kitaura, Y.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1997

fDate

4-7 Oct. 1997

Firstpage

109

Lastpage

112

Abstract

The stacked DCFL (direct coupled FET logic) structure makes it possible to have supply voltage compatibility to Si LSIs with IC circuit current reduction. The idea is to stack DCFL circuits by utilizing the Schottky FET characteristic, which makes the total DCFL circuit current hold constantly independent of any logic conditions. This circuit structure was applied to the divide by 64/65 or 128/129 prescalar IC, which operates at 2.5 GHz on a supply voltage of 3 V with circuit current of 9.8 mA. Virtual ground stability was investigated to apply the stacked DCFL to application-specific integrated circuits (ASICs). The stability of the virtual ground was confirmed by modeling the stacked DCFL circuit and simulating the circuit using SPICE.<>

Keywords

SPICE; application specific integrated circuits; direct coupled FET logic; integrated logic circuits; large scale integration; logic CAD; 2.5 GHz; 3 V; 9.8 mA; ASICs; IC circuit current reduction; LSIs; SPICE; Schottky FET characteristic; application-specific integrated circuits; circuit current; logic conditions; prescalar IC; stability; stacked DCFL structure; supply voltage compatibility; virtual ground; Application specific integrated circuits; BiCMOS integrated circuits; FETs; Frequency conversion; Gallium arsenide; Integrated circuit modeling; Inverters; Power supplies; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1992. Technical Digest 1992., 14th Annual IEEE

Conference_Location

Miami Beach, FL, USA

Print_ISBN

0-7803-0773-9

Type

conf

DOI

10.1109/GAAS.1992.247211

Filename

247211