DocumentCode :
3388418
Title :
Design and FPGA implementation of flexible and efficiency digital down converter
Author :
Changrui, Wu ; Chao, Kong ; Shigen, Xie ; Huizhi, Cai
Author_Institution :
Inst. of Acoust., Chinese Acad. of Sci., Beijing, China
fYear :
2010
fDate :
24-28 Oct. 2010
Firstpage :
438
Lastpage :
441
Abstract :
Digital down converter (DDC) is the one of the key technologies in the field of software define radio (SDA). Compared with traditional ASIC DDC devices, DDCs implemented by FPGA have more flexible frequency and phase characteristics and higher precision computation. The paper designed and implemented DDC with above advantages on Xilinx FPGA Virtex-5. Through analyzing the key points of DDC theory and MATLAB simulation analysis, DDC with across clock region and FIFO interface characteristics is designed using Xilinx ISE. Some important and practical implementation details are given in this paper. And finally presents one application of DDC in communication systems by the portions given in this document.
Keywords :
field programmable gate arrays; software radio; FIFO interface characteristics; MATLAB simulation analysis; Xilinx FPGA Virtex-5; Xilinx ISE; digital down converter; phase characteristic; software define radio; Clocks; Converters; Field programmable gate arrays; Finite impulse response filter; IP networks; Software; Digital Down Converter; FPGA; Flexible;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing (ICSP), 2010 IEEE 10th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-5897-4
Type :
conf
DOI :
10.1109/ICOSP.2010.5654948
Filename :
5654948
Link To Document :
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