DocumentCode :
3388424
Title :
An improved equalization circuit for 10-Gb/s high-speed serial transmission over backplane channel
Author :
Wang, Bo ; Chen, Dianyong ; Liang, Bangli ; Kwasniewski, Tad
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, ON, Canada
fYear :
2009
fDate :
23-25 July 2009
Firstpage :
369
Lastpage :
372
Abstract :
This paper presents an improved equalization circuit, with a linear equalizer (LE) and a decision feedback equalizer (DFE) in the receiver, for 10-Gb/s high-speed serial data transmission over highly lossy electrical backplane channels. Although DFE provides an effective way to compensate various channel impairments, the pre-cursor inter-symbol interference (ISI) is still a significant problem for channel equalization. With the new equalization method, the pre-cursor ISI is compensated with the linear equalizer, and the post-cursor ISI is cancelled by the DFE. The improved equalization circuit with programmable linear equalizer and a 3-tap DFE is implemented to work at 10-Gb/s and compensate the channel loss of -20 dB. The results show it outperform a traditional 5-tap DFE in vertical eye-opening.
Keywords :
compensation; decision feedback equalisers; intersymbol interference; telecommunication channels; bit rate 10 Gbit/s; channel impairment compensation; decision feedback equalizer; high-speed serial data transmission; lossy electrical backplane channel equalization; pre-cursor inter-symbol interference; programmable linear equalizer; Backplanes; Bandwidth; Decision feedback equalizers; Dielectric losses; Feedback circuits; Frequency; Impedance; Interference; Propagation losses; Transmitters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on
Conference_Location :
Milpitas, CA
Print_ISBN :
978-1-4244-4886-9
Electronic_ISBN :
978-1-4244-4888-3
Type :
conf
DOI :
10.1109/ICCCAS.2009.5250492
Filename :
5250492
Link To Document :
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