Title :
A 1 mW, 500 MHz 4-bit adder using two-phase dynamic FET logic gates
Author :
Nary, K.R. ; Long, S.I.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
A 4-b two-phase dynamic FET logic adder is presented which has been demonstrated to operate up to 740 MHz with an associated power dissipation of only 2.4 mW. AT 500 MHz, the adder dissipates 1 mW. The adder core is composed of 44 TDFL gates, and 72 TDFL inverters are used to form shift registers so that the five bits of a sum are shifted out of the adder on the same clock cycle. It operates from a 1-V supply and ground and two clocks. The adder, including shift registers, occupies only 0.23 mm/sup 2/.<>
Keywords :
adders; field effect integrated circuits; integrated logic circuits; invertors; logic gates; shift registers; 1 mW; 2.4 mW; 500 MHz; 740 MHz; TDFL gates; TDFL inverters; adder; clock cycle; power dissipation; shift registers; two-phase dynamic FET logic gates; Adders; Circuit testing; Clocks; FETs; Frequency; Gallium arsenide; Logic circuits; Logic design; Logic gates; Power dissipation;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1992. Technical Digest 1992., 14th Annual IEEE
Conference_Location :
Miami Beach, FL, USA
Print_ISBN :
0-7803-0773-9
DOI :
10.1109/GAAS.1992.247214
