DocumentCode :
3388469
Title :
FunState-an internal design representation for codesign
Author :
Thiele, L. ; Strehl, K. ; Ziegengein, D. ; Ernst, R. ; Teich, J.
Author_Institution :
Comput. Syst. & Networks Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland
fYear :
1999
fDate :
7-11 Nov. 1999
Firstpage :
558
Lastpage :
565
Abstract :
In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines. It is shown how properties relevant for scheduling and verification of specification models like boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets may be represented in the FunState model. Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model´s state transitions in form of a periodic graph.
Keywords :
Petri nets; data flow analysis; finite state machines; functional programming; hardware-software codesign; scheduling; FunState; Petri nets; boolean dataflow; codesign; communicating state machines; cyclostatic dataflow; functional programming; internal design representation; marked graphs; periodic graph; scheduling; state machines; synchronous dataflow; system components; Computational modeling; Computer networks; Data flow computing; Design engineering; Embedded computing; Embedded system; Functional programming; Petri nets; Processor scheduling; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-7803-5832-5
Type :
conf
DOI :
10.1109/ICCAD.1999.810711
Filename :
810711
Link To Document :
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