Title :
25 ps/gate GaAs standard cell LSIs using 0.5 mu m gate MESFETs
Author :
Nemoto, M. ; Ogawa, Y. ; Morita, Y. ; Seki, S. ; Kawakami, Y. ; Akiyama, M.
Author_Institution :
Oki Electric Ind. Co. Ltd., Tokyo, Japan
Abstract :
A design system of GaAs standard cell LSIs using 0.5- mu m MESFETs is presented. This design system is intended to be used to design LSIs whose operating speed is from several hundred MHz to several GHz. A basic gate is DCFL (direct coupled FET logic), and the delay time is less than 25 ps. The library includes 40 cells and 8 I/O buffers which are designed to be compatible with ECL 10 K, TTL (transistor-transistor logic), CMOS, and GaAs. Using this design system, an LSI was fabricated, and its performance was evaluated. The results of the evaluation show that the error in postlayout simulation is under 10%.<>
Keywords :
cellular arrays; direct coupled FET logic; gallium arsenide; integrated logic circuits; large scale integration; 0.5 micron; CMOS; DCFL; ECL; GaAs; I/O buffers; MESFETs; TTL; delay time; operating speed; postlayout simulation; standard cell LSIs; Delay effects; FETs; Gallium arsenide; Large scale integration; Logic devices; MESFETs; Temperature dependence; Temperature distribution; Temperature measurement; Threshold voltage;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1992. Technical Digest 1992., 14th Annual IEEE
Conference_Location :
Miami Beach, FL, USA
Print_ISBN :
0-7803-0773-9
DOI :
10.1109/GAAS.1992.247215
