GaAs RISC processors

Author

Brown, R.B. ; Barker, P. ; Chandna, A. ; Huff, T.R. ; Kayssi, A.I. ; Lomax, R.J. ; Mudge, T.N. ; Nagle, D. ; Sakallah, K.A. ; Sherhart, P.J. ; Uhlig, R. ; Upton, M.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

fYear

1997

fDate

4-7 Oct. 1997

Firstpage

81

Lastpage

84

Abstract

A simplified version of a RISC (reduced instruction set computer) microprocessor has been implemented with E/D MESFET DCFL (direct coupled FET logic) in the Vitesse HGaAs II process. This chip was designed to drive the development of digital GaAs design automation tools. The processor architecture was modified to fit DCFL technology. The 60,500-transistor circuit executes a set of 29 basic instructions. It dissipates 11 W and operates at over 100 MHz.<>

Keywords

III-V semiconductors; Schottky gate field effect transistors; direct coupled FET logic; gallium arsenide; microprocessor chips; reduced instruction set computing; 11 W; E/D MESFET DCFL; RISC processors; Vitesse HGaAs II process; design automation tools; processor architecture; Computer aided instruction; Computer architecture; Coupling circuits; Design automation; FETs; Gallium arsenide; Logic; MESFETs; Microprocessors; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1992. Technical Digest 1992., 14th Annual IEEE

Conference_Location

Miami Beach, FL, USA

Print_ISBN

0-7803-0773-9

Type

conf

DOI

10.1109/GAAS.1992.247218

Filename

247218