A 125-MHz wide-range mixed-voltage I/O buffer using gated Floating N-well circuit

Author

Wang, Chua-Chin ; Liao, Szu-Chia ; Liu, Yi-Cheng

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

3421

Lastpage

3424

Abstract

A fully bidirectional mixed-voltage I/O buffer using a gated Floating N-well circuit is presented. In addition, to provide appropriate gate voltages for Output stage, a Dynamic gate bias generator without gate-oxide overstress effect is implemented. The proposed I/O also takes advantage of a novel Gate-tracking circuit and a PAD voltage detector by means of eliminating the leakage current such that the compatibility among all subcircuits is ensured. Our design is proved on silicon that when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, the maximum data rate is found to be 80/80/125/100/80 MHz, respectively, with a given capacitive load of 10 pF.

Keywords

buffer circuits; integrated circuit design; PAD voltage detector; bidirectional mixed-voltage I/O buffer; dynamic gate bias generator; frequency 125 MHz; frequency 80 MHz; gate-oxide overstress effect; gate-tracking circuit; gated floating N-well circuit; leakage current; voltage 0.9 V; voltage 1.2 V; voltage 1.8 V; voltage 3.3 V; voltage 5.0 V; Circuits; dynamic gate bias; floating N-well; mixed-voltage; wide-range I/O buffer;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537865

Filename

5537865