Arbitrary precision arithmetic-SIMD style

Author

Balakrishnan, S. ; Nandy, S.K.

Author_Institution

Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India

fYear

1998

fDate

4-7 Jan 1998

Firstpage

128

Lastpage

132

Abstract

Current day general purpose processors have been enhanced with what is called “media instruction set” to achieve performance gains in applications that are media processing intensive. The instruction set that has been added exploits the fact that media applications have small native datatypes and have widths much less than that supported by commercial processors and the plethora of data-parallelism in such applications. Current processors enhanced with the “media instruction set” support arithmetic on sub-datatypes of only 8-bit, 16-bit, 32-bit and 64-bit precision. In this paper we motivate the need for arbitrary precision packed arithmetic wherein the width of the sub-datatypes are programmable by the user and propose an implementation for arithmetic on such packed datatypes. The proposed scheme has marginal hardware overhead over conventional implementations of arithmetic on processors incorporating a multimedia extended instruction set

Keywords

digital arithmetic; instruction sets; multimedia computing; parallel processing; 8 to 64 bit; SIMD style; arbitrary precision arithmetic; data-parallelism; marginal hardware overhead; media instruction set; media processing intensive; native datatypes; packed datatypes; Arithmetic; Computer aided instruction; Concurrent computing; Electronic mail; Hardware; High performance computing; Performance gain; Pixel; Registers; Supercomputers;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Conference_Location

Chennai

ISSN

1063-9667

Print_ISBN

0-8186-8224-8

Type

conf

DOI

10.1109/ICVD.1998.646590

Filename

646590