Automatic test pattern generation for improving the fault coverage of microprocessors

In order to improve the quality of microprocessor tests, the use of instruction sets for testing is indispensable. In this paper, we will present a new method consisting of the automatic generation of a functional test pattern, formed by a combination of instructions sets and enabling the efficient improvement of the fault coverage. With this method, a test pattern is first generated to test all of an S number of instruction mnemonics. Then, for the faults that were undetected by that test pattern, an L number of sets of K number of instructions are drawn from the S number of instructions, and the set enabling the efficient improvement of the fault coverage is selected. By repeating this procedure, a high fault coverage can be obtained with a short test pattern. The effectiveness of our method was proved by the results of experiments obtained with the software that was created based on this method