Optimizing nanoscale MOSFET architecture for low power analog/RF applications

Author

Ghosh, Debashis ; Parihar, Manoj Singh ; Kranti, Abhinav

Author_Institution

Low Power Nanoelectron. Res. Group, Indian Inst. of Technol., Indore, Indore, India

fYear

2013

fDate

2-4 Jan. 2013

Firstpage

22

Lastpage

23

Abstract

This work reports on possible ways of improving analog/RF performance metrics, through device structure optimization, for low power applications. It is shown that underlap source/drain (S/D) design and junctionless transistor architecture can both yield improved analog/RF figures of merit in comparison to conventional abrupt source/drain MOSFETs. Junctionless devices overcome the gain-bandwidth trade-off associated with analog design. The results are significant for RFICs in emerging ultra-low-power technologies.

Keywords

MOSFET; analogue integrated circuits; low-power electronics; nanoelectronics; optimisation; radiofrequency integrated circuits; RFIC; analog design; analog/RF performance metrics; device structure optimization; junctionless devices; junctionless transistor architecture; low power analog/RF applications; nanoscale MOSFET architecture; ultra-low-power technologies; underlap source/drain design; Conferences; Decision support systems; Nanoelectronics; analog/RF and Double Gate MOSFET; junctionless; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanoelectronics Conference (INEC), 2013 IEEE 5th International

Conference_Location

Singapore

ISSN

2159-3523

Print_ISBN

978-1-4673-4840-9

Electronic_ISBN

2159-3523

Type

conf

DOI

10.1109/INEC.2013.6465941

Filename

6465941