• DocumentCode
    3388839
  • Title

    Easily path delay fault testable non-restoring cellular array dividers

  • Author

    Sidiropoulos, G. ; Vergos, H.T. ; Nikolos, D.

  • Author_Institution
    Dept. of Comput. Eng. & Inf., Patras Univ., Greece
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    47
  • Lastpage
    52
  • Abstract
    Testing of N×N Non-Restoring Cellular Array Dividers (NRCAD) with respect to path delay faults, is studied in this paper. Design modifications are proposed and a path selection method is suggested. We prove that the selected paths are Single Path Propagating Hazard Free Robustly Testable (SPP-HFRT) and that by measuring their delays the delay along any other path of the divider can be easily calculated. The number of selected paths is impressively small compared to all paths of the divider. The delay overhead of the modified design for all values of N is negligible, while the hardware overhead is small too. This is the first easily testable, with respect to path delay faults, NRCAD design in the open literature
  • Keywords
    cellular arrays; combinational circuits; delay circuits; delay estimation; design for testability; dividing circuits; fault diagnosis; logic testing; NRCAD design; delay measurement; delay overhead; design modifications; hardware overhead; path delay fault testable nonrestoring cellular array dividers; path delay faults; path selection method; single path propagating hazard free robustly testable paths; Argon; Circuit faults; Circuit testing; Electrical fault detection; Electronic switching systems; Fault detection; Integrated circuit modeling; Manufacturing processes; Propagation delay; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian
  • Conference_Location
    Shanghai
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-0315-2
  • Type

    conf

  • DOI
    10.1109/ATS.1999.810728
  • Filename
    810728