Title :
March tests for word-oriented two-port memories
Author :
Hamdioui, Said ; van de Goor, A.J.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
This paper presents an approach for testing word-oriented multi-port memories. Fault models for such memories are given based on fault models for bit-oriented multi-port memories. A distinction between intra-word faults and inter-word faults as made. A systematic way of converting bit-oriented multi-port memory tests into word-oriented multi-port memory tests is presented
Keywords :
cellular arrays; fault diagnosis; fault simulation; integrated circuit testing; integrated memory circuits; two-port networks; bit-oriented multi-port memory tests; fault models; inter-word faults; intra-word faults; march tests; word-oriented two-port memories; Bills of materials; Computer architecture; Educational institutions; Electronic mail; Information technology; Read-write memory; System testing;
Conference_Titel :
Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian
Conference_Location :
Shanghai
Print_ISBN :
0-7695-0315-2
DOI :
10.1109/ATS.1999.810729
