A 14-bit 250MS/s digital to analog converter with binary weighted Redundant Signed Digit coding

It is well known that the performance of current-steering D/A converters (DACs) is affected by parasitic effects such as static device mismatch and dynamic timing mismatch. Typically, this results into about 10-bit peak performance. To increase this number, the designer has two options: either use a very large silicon area to obtain better matching, or alternatively use a (sophisticated) calibration technique. In this paper we present a D/A converter circuit with a “Redundant Signed Digit” (RSD) coding scheme for binary weighted D/A conversion. This scheme does not really improve the peak performance for full-scale input signals. E.g with a full-scale 3.2 MHz 14-bit input sinusoidal signal, the SFDR equals 60 dB for our circuit. But the performance is only gradually reduced for small input signals: for a -43 dB 14-bit input signal the SFDR is still 44 dB, which is close to the performance of an ideal 14-bit D/A converter. The analog section of this circuit was implemented in a standard 0.18 m (1P6M) CMOS process and requires only 0.1 mm² of silicon area.