Analysis of gate capacitances in GaAs JFETs

Using two-dimensional simulations, the gate capacitances of n-channel, p-barrier GaAs junction field effect transistors (JFETs) fabricated with ion-implantation and diffused-junction technologies are analyzed. In addition to channel, fringe, and pad capacitances which are also present in GaAs MESFETs, JFETs have sidewall capacitances and a capacitance due to the effective increase in the gate length caused by the lateral spreading of the p dopants. Both of these capacitances can be minimized by reducing the depth of the p region. Sidewall capacitance can be nearly eliminated if the p region depth is less than the depth of the surface depletion in the n region beside the gate. The results are compared with RF data for ion-implanted JFETs.<>