An accurate logic threshold voltages determination model for CMOS gates to facilitate test generation and fault simulation

In this paper we present an accurate and efficient modeling technique for CMOS circuits to facilitate the implementation of test generation (TG) and fault simulation (FS). The model is more general than any previous model. The accuracy is achieved because the device parameters, circuit configuration, and test patterns are considered. The efficiency is achieved due to the simplicity of the solution methods that require no complex circuit level simulation and any empirical constant. By using this model the “Byzantine General” problem during the FS and TG can be overcome. Experimental data show that SPICE like accuracy can be achieved without carrying out circuit-level simulation