3D NoCs — Unifying inter & intra chip communication

Author

Loi, Igor ; Marchal, Pol ; Pullini, Antonio ; Benini, Luca

Author_Institution

DEIS, Univ. of Bologna, Bologna, Italy

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

3337

Lastpage

3340

Abstract

Networks-on-chip have been developed in the last few years to address the scalability challenges of global on-chip communication. VLSI technology is now rapidly moving into vertical stacking to overcome fundamental communication and integration bottlenecks, however this technology is not mature yet, and significant reliability challenges must be overcome. In this paper we describe our effort in establishing a 3DNoC design flow and in designing circuits and architectural solutions for variability and reliability characterization and tolerance.

Keywords

VLSI; integrated circuit design; integrated circuit reliability; network-on-chip; three-dimensional integrated circuits; 3D NoC design flow; VLSI technology; circuit architecture; circuit design; global on-chip communication; inter chip communication; intra chip communication; network-on-chip; reliability; scalability challenge; Fault tolerance; Integrated circuit interconnections; Integrated circuit reliability; Integrated circuit technology; Network topology; Network-on-a-chip; Scalability; Stacking; Through-silicon vias; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537895

Filename

5537895