Title :
A parallel generation system of compact IDDQ test sets for large combinational circuits
Author :
Shinogi, Tsuyoshi ; Hayashi, Terumine
Author_Institution :
Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
Abstract :
This paper presents a high performance compact IDDQ test generation system for detecting bringing faults, targeting large circuits. This system is based on the iterative-improvement-based method. We use a two-level parallel processing technique for speeding up the test generation significantly and invoke the assist of a deterministic ATPG for attaining 100% fault efficiency. The experimental results demonstrate its effectiveness
Keywords :
CMOS logic circuits; automatic test pattern generation; combinational circuits; electric current measurement; fault diagnosis; integrated circuit testing; iterative methods; logic testing; parallel processing; CMOS circuits; bringing fault detection; compact IDDQ test generation system; compact IDDQ test sets; deterministic ATPG; fault efficiency; iterative-improvement-based method; large combinational circuits; parallel generation system; test generation speed-up; two-level parallel processing technique; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Logic testing; Parallel processing; Power supplies; System testing;
Conference_Titel :
Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian
Conference_Location :
Shanghai
Print_ISBN :
0-7695-0315-2
DOI :
10.1109/ATS.1999.810746
