Title :
PWL cores for nonlinear array processing
Author :
Di Federico, Martín ; Julián, Pedro ; Mandolesi, Pablo S. ; Andreou, Andreas G.
fDate :
May 30 2010-June 2 2010
Abstract :
This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broadcast the parameters stored in the memory, and in addition, row and column operations can be serialized. Based on a 90nm technology process, the different options will be analyzed and compared using simulations.
Keywords :
VLSI; array signal processing; cellular neural nets; parallel processing; piecewise linear techniques; random-access storage; 90nm technology process; PWL cores; SIMD processors; VLSI cell; cellular neural networks; nonlinear array processing; nonlinear neuronal array; simplicial piecewise linear operation; size 90 nm; Arithmetic; Array signal processing; CMOS technology; Cellular neural networks; Computational modeling; Microprocessors; Photodiodes; Piecewise linear techniques; Standards development; Very large scale integration;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537906
