Title :
Communication-aware application mapping and scheduling for NoC-based MPSoCs
Author :
Yu, Heng ; Ha, Yajun ; Veeravalli, Bharadwaj
Author_Institution :
Dept. of ECE, Nat. Univ. of Singapore, Singapore, Singapore
fDate :
May 30 2010-June 2 2010
Abstract :
Combined computation and communication workload mapping and scheduling pose a major challenge in embedded NoC-based MPSoC design. While contemporary researches largely focus on data locality-centric mapping methodologies, unawareness of transmission route and timing may negatively impact the mapping efficiency. In this paper, we develop a unified communication-aware NoC-based MPSoC mapping and scheduling algorithm, in which a list-scheduling method is used to map prioritized tasks to the best fit processor, based on a transmission route-aware cost function. Our algorithm is able to realize precise and predictable packet routing in the process of task mapping, and achieve shorter end-to-end application execution time. To evaluate our algorithm, we conduct experiments using three real applications on a simulated NoC-based MPSoC platform. Comparison results show that our algorithm can achieve greatly improved overall end-to-end time, and about 38.3% less transmission time on a 3×3 mesh structure.
Keywords :
multiprocessing systems; network-on-chip; scheduling; MPSoC; communication workload mapping; communication-aware application mapping; list-scheduling method; mapping efficiency; multiprocessor system-on-chip; network-on-chip; packet routing; transmission route-aware cost function; workload scheduling; Computer architecture; Data communication; Embedded computing; Multiprocessing systems; Network-on-a-chip; Processor scheduling; Routing; Runtime; Scheduling algorithm; Timing;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537920