Defect level prediction using multi-model fault coverage

Continuous progress in VLSI technologies keeps reducing the defect density. However; a yield of 100% is considered unlikely. It is also known that VLSI circuits can never be “completely” tested. Therefore, defect level cannot be reduced to zero. The quality of a test is usually evaluated by the fault coverage. The relationship between the defect level and the fault coverage has never been proposed. In this paper; we first propose the concept of multi-model fault coverage (MFC) instead of the fault coverage based on a unique fault model. The relationship between defect level, fabrication yield, and multi-model fault coverage is then derived. We also analyze the defect level error between the predicted defect level and the physical defect level. As the number of fault models used increases, the defect level error can be reduced significantly. Our approach is very effective for product quality prediction and the concept of multi-model fault coverage is very useful for today´s system-on-chip technology