Asynchronous BFT for low power networks on chip

Author

Abd El-Ghany, Mohamed A ; El-Moursy, Magdy A. ; Korzec, Darek ; Ismail, Mohammed

Author_Institution

Electron. Eng. Dept., German Univ. in Cairo, Cairo, Egypt

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

3240

Lastpage

3243

Abstract

Asynchronous Butterfly Fat Tree (BFT) architecture is proposed to achieve low power Network on Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (α_data) satisfies a certain condition. The area of Asynchronous BFT switch is increased by 25% as compared to Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by up to 33% as compared to the power dissipation of the conventional Synchronous architecture when the α_data equals 0.2 and the activity factor of the control signals is equal to 1/64 of the α_data. The total metal resources required to implement Asynchronous design is decreased by 12%.

Keywords

computer architecture; integrated circuit design; low-power electronics; network-on-chip; asynchronous BFT; asynchronous butterfly fat tree architecture; asynchronous design; data transfer; low power network on chip; power dissipation; synchronous architecture; synchronous switch; Clocks; Decoding; Graphics; Integrated circuit interconnections; Network-on-a-chip; Power dissipation; Power engineering and energy; Switches; Telecommunication network reliability; Topology; BFT; GALS; Low Power; NoC;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537922

Filename

5537922