An all-digital PLL with a first order noise shaping Time-to-Digital Converter

This paper presents an All Digital PLL (ADPLL) based on a first order noise shaping Time-to-Digital Converter (TDC). The architectures of two state-of-art ADPLLs and a state-of-art Gated Ring Oscillator (GRO) TDC are described. The architecture of the GRO TDC is compared with that of the proposed Local Oscillator based TDC (LO TDC) in terms of spectral performance. Behavioral Verilog-AMS models of the LO, exact LO, and exact GRO TDCs are described briefly. Finally, the Verilog-AMS models of three ADPLLs, including the TDC models, are compared by means of simulations.